1. Field of the Invention
The present invention relates to a driving device for a display apparatus and, more particularly, to a driving device for a display apparatus including a gamma correction function for correcting gray scales of video signals independently for each of three primary colors (red, green and blue).
2. Description of the Related Art
FIG. 6 shows the construction of a conventional liquid crystal display apparatus module. The liquid crystal display apparatus module includes multiple source drivers 51 and gate drivers 52 for directly driving a liquid crystal panel 54 and a controller 56 for supplying drive signals to the drivers 51 and 52.
Each of the source drivers 51 and gate drivers 52 is an LSI device and is provided in a tape carrier package (TCP) 53. The TCP's 53 are implemented in the liquid crystal panel 54.
On the other hand, the controller 56 and wires connecting between the controller 56 and the drivers 51 and 52 are provided on a flexible substrate 55, which is different from the liquid crystal panel 54.
The liquid crystal panel 54 displays by drive signals supplied to source bus lines and gate bus lines, not shown. The source drivers 51 drive the source bus lines. The gate drivers 52 drive the gate bus lines.
In FIG. 6, each of the source drivers 51 is rectangular. Wires extending from the above in FIG. 6 are input lines for signals input from the controller circuit 56. Many wires extending from the bottom of the rectangular source driver 51 are output lines to the liquid crystal panel 54.
FIG. 7 is a plan view showing a layout of terminals of the source driver 51 of the conventional liquid crystal display apparatus module. In FIG. 7, a driving circuit element region 40 is located at the center of the rectangular source driver 51. Many electrode pads 100 are provided along four sides of the rectangle.
In FIG. 7, the electrode pads for output terminals 41 are provided along the left, right and upper sides of the rectangle. Power supply terminals 42, input control terminals 43 and reference power supply terminals 44 are provided along the bottom side of the rectangle.
Gold bumps, not shown, are plated on each of the electrode pads 100. Each of the gold bumps is about 40 to 90 μm long and wide and about 10 to 20 μm high.
FIG. 8 is a schematic diagram of component circuit blocks in the driving circuit element region 40 of the conventional source driver. The circuit blocks of the source driver 51 are mainly a shift register circuit 61, a data latch circuit 62, a sampling memory circuit 63, a hold memory circuit 64, a reference voltage generating circuit 65, a D/A converter circuit 66 and an output circuit 67.
Here, each of the circuit blocks is separately modularized and is laid out in one LSI in general. The LSI is designed generally by using circuit blocks each registered as a macro cell for the CAD design. When the macro cells are reused and the circuit blocks are laid out together as many as possible, operation within each of the circuit blocks is stabilized. Thus, the LSI can operate in accordance with the design specification.
The circuit blocks are laid out such that wires between the circuit blocks within the driving circuit element region 40 and wires between surrounding terminals and the circuit blocks can be the shortest possible.
The source driver 51 includes many output terminals 41, and must be mounted in a narrower frame region of the liquid crystal panel 54. Thus, the source driver 51 has a significantly long and narrow chip form.
In view of the above-mentioned wires and limitations, the conventional source driver 51 in FIG. 8 has the reference voltage circuit 65 and data latch circuit 62 for processing analog voltage at the center of the chip. The rest of the circuit blocks are located at the left and right symmetrically. Thus, an equivalent amount of effect from wire resistance and so on can be given on each of the circuit blocks.
In each of the gate drivers 52, circuit blocks are laid out in view of wires and so on like each of the source drivers 51.
Terminals of indium tin oxide (ITO) are located on the liquid crystal panel 54. The ITO terminals are electrically connected to the output terminals to the liquid crystal panel 54 side of the source driver 51 and gate driver 52 through the wires on the TCP 53.
The ITO terminals and the wires on the TCP 53 are thermally press-fitted and are electrically connected through an anisotropic conductive film (ACF).
The terminals to the flexible substrate 55 within the source driver 51 and gate driver 52 are electrically connected to wires on the flexible substrate 55 through wires on the TCP's 53 by the ACF or soldering.
As described above, signal lines output from the controller circuit 56 are connected to the terminals of the source drivers 51 and gate drivers 52 by using the wires on the flexible substrate 55. The output signal lines from both of the drivers 51 and 52 are connected to the ITO terminals on the liquid crystal panel 54 through the wires on the TCP's 53.
Display data signals (three signals of R, G and B), different kinds of control signals and power supplies (GND and VCC) are supplied from the controller circuit 56 to each of the source drivers 51 through the wires. Different kinds of control signals and power supplies are supplied to each of the gate drivers 52 through the wires.
The construction shown in FIG. 6 includes eight source drivers 51 (S1 to S8) and two gate drivers 52 (G1 and G2). Each of the source drivers 51 includes the same circuit blocks. Display data signals (R, G and B), start pulse input signals SSPI and clock signals SCK are supplied from the controller circuit 56 to each of the source drivers 51.
Each of the two gate drivers 52 includes the same circuit blocks. Clock signals GCK and start pulse input signals GSPI are supplied from the controller circuit 56 to each of the gate drivers 52.
FIG. 9 is an explanatory diagram of output terminals of the conventional controller circuit 56. Here, nine output terminals R1 to R6 to SCK are connected to the source drivers 51. Four output terminals from GCK to GSPI are connected to the gate drivers 52.
The terminals R1 to R6, G1 to G6, and B1 to B6 output display data signals R, G and B of 6 bits each, respectively. The terminal LS outputs latch signals. Nine terminals Vref1 to Vref9 output halftone reference voltages to be supplied to the source drivers 51. Similarly, the lower two terminals Vref1 and Vref2 output reference voltages to the gate drivers 52.
When 1024×768 pixels are provided in the liquid crystal panel 54 for each of the three primary colors, the source side (the horizontal direction in FIG. 6) has 1024 pixels ×3 in total. The gate side (the vertical direction in FIG. 6) has 768 pixels.
Here, when the eight source drivers 51 (S1 to S8) drives the pixels of the source side (1024 pixels ×3), each of the source drivers 51 is responsible for 128 pixels ×3 (RGB). Each color includes 6-bit display data signals (R1 to R6, for example). Thus, each of the source drivers 51 displays 64 gray scales.
FIG. 10 is a diagram functionally showing an construction of the circuit blocks of the conventional source driver 51 shown in FIG. 7. The source driver 51 includes the seven functional circuit blocks as shown in FIG. 7.
As shown in FIG. 10, the source driver 51 includes input terminals from SSPin to Vref1 to Vref9 on the left and output terminals SSIO on the right and X0-1 to Z0-128 at the bottom.
Operation of the first source driver 51 will be described, for example.
A start pulse input signal SSPI is input from the controller circuit 56 to the SSPin terminal of the source driver 51. The SSPI signal is synchronized with horizontal synchronous signals of display data signals R, G and B. A clock signal SCK is input to the input terminal SSKin. The shift register circuit 61 uses the clock signal SCK to shift (propagate) the start pulse input signal SSPI and outputs it to the output terminal SSIO as an SSPO signal.
The start pulse input signal SSPI shifted by the shift register circuit 61 is sequentially transferred to the shift register circuits 61 upto the eighth source driver S8. On the other hand, display data signals R, G and B, of 6 bits each, output from the terminals R1 to R6, terminals G1 to G6 and terminals B1 to B6, respectively, of the controller circuit 56 are synchronized with a rising edge of an invert signal (/SCK) of the clock signal SCK and are input to the input terminals R1in to R6in, input terminals G1in to G6in and input terminals B1in to B6in, respectively, of the source driver 51 in series. The display data signals R, G and B are latched in the data latch circuit 62 temporarily and then are sent to the sampling memory circuit 63.
The sampling memory circuit 63 samples the display data signals (that is, R, G and B signals of 6 bits each and 18 bits in total) sent in a time-division manner, from output signals of stages of the shift register. The sampling memory circuit 63 stores the display data signals until a latch signal LS is input from the controller circuit 56 to the hold memory circuit 64.
When the latch signal LS is input to the hold memory circuit 64, the display data stored in the sampling memory circuit 63 is input to the hold memory circuit 64. Thus, the display data signals for one horizontal period of the display data signals R, G and B are latched, that is, are held.
When the display data signals for the next one horizontal period are input from the sampling memory circuit 63, the held display data signals are output to the D/A converter circuit 66.
Halftone reference voltages output from the terminals Vref1 to Vref9 of the controller circuit 56 are input to the terminals Vref1 to Vref9 of the source driver 51 in FIG. 10 and are supplied to the reference voltage generating circuit 65. The reference voltage generating circuit 65 generates 64 levels of gray-scale display reference voltage based on the reference voltages by using a resistance dividing circuit, for example.
The D/A converter circuit 66 converts the R, G and B display data signals (digital) of 6 bits each input from the hold memory circuit 64 to analog signals accordingly and outputs to the output circuit 67. The output circuit 67 amplifies the 64 level analog signals and outputs to terminals, not shown, of the liquid crystal panel 54 through the output terminals Xo-1 to Xo-128, Yo-1 to Yo-128 and Zo-1 to Zo-128. The output terminals Xo-1 to Xo-128, Yo-1 to Yo-128 and Zo-1 to Zo-128 correspond to R, G and B display data signals, respectively, and each of the output terminal sets Xo, Yo and Xo includes 128 terminals.
The terminal VCC and terminal GND of the source driver 51 are terminals for power supply connected to the terminal VCC and terminal GND of the controller circuit 56. Power supply voltage and ground potential are supplied to the terminal VCC and terminal GND of the source driver 51, respectively.
FIG. 11 is a schematic block diagram showing a construction of the inside of the conventional reference voltage generating circuit 65. FIG. 12 is a schematic diagram showing a construction of the conventional D/A converter 66 and the output circuit 67. These circuits 65, 66 and 67 convert and output display data (Bit0 to Bit 5 in FIG. 12) supplied as digital signals to analog voltage values.
The D/A converter circuit 66 selects and outputs one of the 64 gray-scale display reference voltages generated by the reference voltage generating circuit 65. The D/A converter circuit 66 includes a MOS transistor. The output circuit 67 includes a so-called voltage follower circuit.
In FIG. 12, the output circuit 67 outputs the analog voltage value selected by the D/A converter circuit 66 of the 64 level analog voltages corresponding to the values of the supplied display data (Bit0 to Bit5).
The output circuit 67 reduces the impedance of the voltage selected by the D/A converter circuit 66 and outputs to the liquid panel side through the terminals (Xo-1 to Xo-128 and so on) for outputting liquid crystal driving voltage shown in FIG. 10.
Here, typically, the reference voltage generating circuit 65 is commonly used for the multiple terminals for outputting liquid crystal driving voltages. However, one D/A converter circuit 66 and one output circuit 67 are used for each of the terminals for outputting liquid crystal driving voltages.
Furthermore, for color display, the terminals for outputting liquid crystal driving voltages are used for colors, respectively. The D/A converter circuit 66 and output circuit 67 display one color for each pixel. Therefore, one D/A converter circuit 66 and one output circuit 67 are used for each color.
In other words, when the liquid crystal panel 54 includes 3N pixels horizontally, N terminals for outputting liquid crystal driving voltages are used each of red R1 to RN, green G1 to GN and blue B1 to BN. That is, 3N terminals for outputting liquid crystal driving voltages are used in total. Therefore, 3N D/A converter circuits 66 and 3N output circuits 67 are required.
The reference voltage generating circuit 65 shown in FIG. 11 has nine halftone voltage input terminals (Vref1 to Vref9) and resistance elements (R0 to R7) having resistance ratios for γ correction and being connected in series.
The resistance elements R0, R1, . . . and R7 are represented as resistances having resistance values in accordance with γ corrections, respectively, in FIG. 11. However, in reality, each of the resistance elements R0 to R7 further includes multiple resistances equally dividing the voltage into eight voltages between halftone voltage terminals Vref into eight. The conventional reference voltage generating circuit 65 generates gray-scale display voltages for the y corrections. One voltage generating circuit 65 is provided in each source driver and is shared by R, G and B processing circuits.
FIG. 13 shows a graph of a gray-scale voltage characteristic in the conventional source driver 51. The horizontal axis indicates gray-scale display data (digital values) input to the source driver 51. The vertical axis indicates analog voltage values (liquid crystal driving output voltages) after γ correction corresponding to the display data.
Here, V0 to V63 in the vertical axis correspond to reference voltages Vref of the reference voltage generating circuit 65. The reference voltages Vref1, Vref2, Vref3, Vref4, Vref5, Vref6, Vref7, Vref8 and Vref9 correspond to V0, V8, V16, V24, V32, V40, V48, V56 and V63, respectively.
The characteristics in FIG. 13 are plotted in the line graph in which the resistance elements for γ correction have different resistance ratios in order to display natural gray scales in view of an optical characteristic of a liquid crystal material.
As shown in FIG. 11, 64 levels (V0 to V63) of gray-scale display reference voltage are output from the reference voltage generating circuit 65. These outputs are input to the D/A converter 66. The D/A converter circuit 66 selects and outputs one of the input 64 levels of reference voltage in accordance with the type of the display data (Bit 0 to Bit5).
As shown in FIG. 12, the D/A converter circuit 66 includes many switches. Each switch includes a MOS transistor. In the D/A converter circuit 66, the switches corresponding to 6-bit digital signals Bit0 to Bit5 are turned ON or OFF in accordance with the values of the 6-bit digital signals Bit0 to Bit5. In accordance with a combination of these switches, one of the input 64 levels of reference voltage is selected and is output.
As described above, the output circuit 67 reduces the impedance of the selected reference voltage by using the voltage follower circuit. This reduction is for charging the pixels and wire capacitance of the liquid crystal panel, and increasing speed for leading the driving voltage to a predetermined voltage.
The source driver 51 having the above-described construction and performing the above-described operation has a large number of output terminals as shown in FIG. 8. These output terminals and terminals of the liquid crystal panel 54 must be connected through the shortest possible wires efficiently. For this purpose, the source driver 51 is laid out such that the upper long side of the rectangular source driver 51 having the output terminals 41 in FIG. 8 can face against the liquid crystal panel 54. The lower long side in FIG. 8 has the power supply terminals 42 and so on. This lower long side does not face against the liquid panel 54.
On the other hand, as shown in FIG. 6, multiple source drivers are cascade-connected. A start pulse signal is transferred sequentially from one source driver to another.
Therefore, in the lay-out of the circuit blocks in the source driver 51, in view of a signal processing flow, the shift resistor circuits 61 are laid out in parallel at the lower long side, which does not face against the liquid crystal panel 54.
Signals pass through the sampling memory circuit 63, the hold memory circuit 64, the D/A converter circuit 66 and the output circuit 67 in order. Thus, as shown in FIG. 8, these circuit blocks are laid out in a direction perpendicular to the chip long side.
Presently, a liquid crystal display apparatus having higher resolution and larger screen is demanded. In addition, the cost reduction is requested. As the size of a screen is increased, the number of pixels of a panel is increased. As a result, the number of output terminals handled by one source driver increases.
In order to meet the request for the cost reduction, the number of source drivers must be reduced. In order to reduce the number of source drivers, the number of output terminals included in one source driver must be increased.
As for the respective circuit block of the source driver such as source driver 51, one circuit block corresponds to one output except for the reference voltage generating circuit 65. Therefore, as the number of output terminals 41 increases, the number of circuits increases. As the number of output terminals 41 increases, the number of levels of the shift resistor circuit 61 increases. Thus, the shift register circuit 61 has a long and narrow layout. Also, the other circuit blocks are laid out in a horizontally oriented form.
Furthermore, when the number of output terminals 41 of the source driver 51 increases, the length of the long side of the chip is increased. Therefore, the chip becomes significantly long and narrow. For example, when bumps of the chip and inner leads of a tape base are electrically connected to be a TCP, difficulties in chip handling, height control between the chip and the inner leads of the tape base and control over the pitch precision of the inner leads are increased.
In order to avoid these kinds of inconvenience and in order to achieve the increase in the number of output terminals, an increase in ratio of the long side to the short side must be suppressed.
On the other hand, improved quality of liquid crystal display is also requested strongly with respect to γ correction.
As described above, in order to achieve the natural gray-scale display, γ correction is performed in accordance with an optical characteristic of a liquid crystal material. The γ correction depends on voltage-transmissivity characteristic (V-T characteristic) of each liquid crystal display device. However, the V-T characteristic varies largely in producing liquid crystal display devices. The V-T characteristic differs largely for each liquid crystal display device. Determining a resistance ratio uniquely for γ correction is difficult. Thus, it is difficult to maintain constant quality with respect to γ correction.
The V-T characteristic may also depend on variation of each light incident on a liquid crystal display device and variation of characteristics of an optical system, etc.
Therefore, increasing the screen size and resolution an increase in the number of pixels. This may be disadvantageous to achieving a more proper gray-scale display.